TCM 3105 PAGE 1 (4-5) FSK MODEM DUAL IN IHE PACKAGE Features (TOP VIEW) Single chip FSK modem. ÚÄÂÄÂÄ¿ Meets CCITT V23 standard: VDD ³1ÀÄÙ ³ OSC2 - Forward channel (Transmit/Receive) CLK ³ ³ 0SC1 at 600/1200 bauds CDT ³ ³ TXD - Backward channel (Transmit/Receive) RXA ³ ³ TXR1 at 75 bauds. TRS ³ ³ TXR2 Meets Bell 202 standards: RXT ³ ³ TXA - Forward channel (Transmit/Receive) RXB ³ ³ CDL at 1200 bauds RXD ³8 9³ VSS - Backward channel(Transmit/Receive) ÀÄÄÄÄÄÙ at 5/150 bauds. TCM3105J OR TCMJ105N Full duplex operation up to 1200 bauds Transmit and receive in 4 wire mode. Carrier detect level adjustment and carrier fail output. SURFACE MOUNT SMALL OUTLINE PACKAGE On chip Transmit/Receive filtering and (TOP VIEW) group delay equalisation. ÚÄÄÄÄÄ¿ Reliable CMOS silicon gate technology. VDD ³1 24³ OSC2 16 pin DIL package (pin to pin CLK ³ ³ 0SC1 compatible with TCM 3101 ). CDT ³ ³ TXD Local copy/loop back test capability. ³ ³ RXA ³ ³ TXR1 ³ ³ TRS ³ ³ ³ ³ TXR2 RXT ³ ³ TXA ³ ³ RXB ³ ³ CDL RXD ³12 13³ VSS ÀÄÄÄÄÄÙ TCM3105DW TCM 3105 PAGE 2 (4-6) FSK MODEM general description The TCM3105 is a versatile single chip Frequency Shift Keyed (FSK) voiceband modem. It uses silicon gate CMOS technology with switched capacitor filtering techniques.It is pin programmable (using V23 operation and is fully reversible, thereby allowing both forward and backward channels to be used simultaneously). The transmitter is a programmable frequency synthesizer which provides two output frequencies (on TXA), representing the "Marks" and "Spaces" ot the digital signal present on the TXD input. The receive section is responsible tor the demodulation ot the analogue signal appearing at the RXA input and is based on the principle of frequency to voltage conversion. This section contains a Group Delay Equaliser (to correct phase distortion). Automatic Gain Control, Carrier Detect Level adjustment and Bias Distortion adjustment, thereby optimising performance and giving the Iovest possible bit error rate. Carrier detect intormation is given to the system by means ot the carrier detect circuitry which sets a flag on the CDT output if the level ot received in band energy falls below a value set on the CDL input for a specified minimum duration. DW NorJ PACK PACK SYMBOL DESCRIPTION PIH N PIH N 1 1 VDD Positive supply voltage 2 2 CLK A continuous clock signal output 3 3 CDT Carrier Detect Output. A low level output indicates carrier fail 5 4 RXA Receive analogue input. The received line signal must be a.c. coupled to RXA pin 7 5 TRS Transmit Receive standard select. This pin, together with TXR1 and TXR2 set the standar bit rates and mark space frequencies (see fig. 5) 9 6* RXT Receive Test access. The output of the limiter is available on this pin 11 7 RXB Receive bias adjust. External adjustment of the decision threshold of the final comperator to minimise bias distortion is avaiiable 12 8 RXD Receive digital output. The demodulated receved data in positive true logic, logic one is a mark and logic zero a space 13 9 VSS Negative supply voltage, normally ground, connected to substrate 14 10 CDL Carrier detect level adjust. External adjustment of carrier detect threshold is available 16 11 TXA Transmit analogue output. This is the modulated signal and must be a.c. coupled 17 12 TXR2 Bit rate select. These tow pins, together with TRS set the bit rates and mark space frequencies 20 13 TXR1 (see fig. 5) 22 14 TXD Transmit digital input. The input data to the transmitter must be possible true logic. Logic one is a mark, logic zero is a space. The data can be accepted at any speed from zero to the selected speed and may be totally asynchronous 23 15 OSC1 Oscillator connections. The crystal typically 4.4336 MHz PAL is connected to these pins if an 24 16 OSC2 external clock is used OSC2 is left open circuit and the clock connected to OSC1 Pins N 4/6/8/10/15/18/19/21 are connected for the DW package. *Not connected for TCM3105J and TCM3105JE TCM 3105 PAGE 3 (4-7) FSK MODEM TCM 3105 Block Diagram FIG.1 See 3105_1.sch (OrCAD SDT schematic file) absolute maximum ratings Supply voltage VDD 0.3 - 10V Voltage cn any terminal 0.3 - VDD Operating free air temperature range -20...+70 C Storage temperature range -55..+150 C Any Input relative to VDD +0.3V Any Input relative to VSS -0.3V Unless otherwise stated, all voltages are with respect to VSS. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond indicated in the "recommended operating conditions" section of this specification is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. TCM 3105 PAGE 4 (4-8) FSK MODEM recommended operating conditions PARAMETER MIN TYP MAX UNIT VDD supply voltage 4 5 6 V Digital input levels: VIH VDD<5.5V 2.0 VDD V 5.5VÄÄÄÂÄ´ RECEIVER ÃÄÄÄÄÄÄÄ>RXD ³ ÀÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÙ ³ ³ ³ ^ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄCDT ÀÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ³ ^ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ´ MODULATOR ÃÄ>Ä´ ÃÄ>ÄÄ´ AMP ÃÄÄÄÄ>TXA ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ³ FILTER ³ ³ ³ ÀÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÙ FIG.3 The frequency response of the transmit filter is dependent upon the mode selected on the TRS, TXR1, TXR2 inputs. In all modes, the first filter section is a switched capacitor low-pass filter which limits the level of harmonics at its output. (This filter has a switching frequency response which provides optimum characteristics for each transmit frequency). For the 75 150 bauds receive mode and 600 1200 bauds transmit mode, the output of the switched capacitor low-pass filter is applied in turn, to an antialiasing filter, a switched capacitor high-pass filter and equaliser before passing through a smoothing filter, the output of which is the TXA pin. This suppresses receive band frequencies such that they do not appear at TXA. For the 600 1200 bauds receive mode, the output of the switched capacitor low-pass filter is applied to a continous low-pass filter, in order to remove harmonics due to sampling, before outputting the signal on TXA. TCM 3105 PAGE 7 (4-11) FSK MODEM receiver The demodulation function of the receiver is based on the principle of frequency to voltage conversion. The receive section is shown in fig.4 and comprises an antialiasing prefilter, a receive amplifier, group delay equaliser, receive filter, limiter, demodulator, post-demodulator filter and slicer. The receive standard is set by the state of the TRS, TXR1 and TXR2 input. The antialiasing prefilter is a continuous low-pass filter which prevents aliasing, due to the sampling nature of the receive filter and group delay equaliser, of high frequency components of the input signal at RXA. The receive amplifier is of variable gain and its purpose is to maintain a suitable signal output level from the receive filter across the dynamic range of the input signal at RXA. The receive filter is designed to limit the bandwidth of the signal presented to the demodulator, reducing out of band interference and also giving high rejection of backward channel frequencies which are typically present at much higher levels than the received signal. The receive filter achieves this by taking the form of a single band-pass stage when in 5 75 150 bauds receive mode, but in the 600 1200 bauds receive mode an additional high-pass filter stage is placed ahead of it, thereby limiting the effect of the frequencies corresponding to the lower bit rates. RECEIVER ÚÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ³ANTI-ALIASING³ ³ RECEIVE ³ ³ ³ ³ GROUP DELAY ³ RXA>ÄÄ´ PRE-FILTER ÃÄÄ>ÄÄ´AMPLIFIERÃÄ>Ä´ RECEIVE FILTER ÃÄ>Ä´ EQUALIZER ÿ ³ ³ ³( A.G.C.)³ ³ ³ ³ ³³ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÄÄÄÂÄÄÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÙ³ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ<ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ´ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ<ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ³ ÚÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ ÚÄÄÄÄÄÄÄÄ¿ ³ ³ ³ ³ ³ ³ POST ³ ³ ³ ÀÄ´LIMITERÃÄ>ÄÄÂÄÄÄ´ DEMODULATOR ÃÄ>Ä´ DEMODULATOR ÃÄÄÄ>Ä´- ³ ³ ³ ³ ³ ³ ³ FILTER ³ ³ SLICER ÃÄÄÄÄ>RXD ÀÄÄÄÄÄÄÄÙ ³ ÀÄÄÄÄÄÄÂÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÙ Ú>Ä´+ ³ V ^ ³ ³ ³ ³ RXT ³ TRS RXB ³ ÀÄÄÄÄÄÄÄÄÙ FIG.4. The Group Delay Equalizer is a switched capacitor network which corrects for both phase and attenuation distortion introduced by the line and receive filter. The output from the Group Delay Equalizer is measured in order both to feedback to the receive amplifier for automatic gain control and to control the carrier detect flag (CDT). The limiter then converts this analogue signal into a squared FSK modulated signal which is then presented to the demodulator. The demodulator, which is an edge triggered multivibrator, performs the frequency to voltage conversion which allows to extract the transmitted data from the modulated signal. The monostable triggers on both the positive and negative going edge of the limited signal, thus producing at its output, a stream of fixed lenght pulses at a frequency which is double that ot the limited input signal. The dc component of this signal is inversely proportional to the received frequency and is extracted by a switched capacitor, low-pass, post demodulator filter. The output analogue signal of the post demodulator filter must be converted into a binary signal by the slicer. TCM 3105 PAGE 8 (4-12) FSK MODEM This is performed by a comparator whose reference and therefore decision threshold is externally set, by input, to the midpoint of the analogue signal. (The midpoint is defined as that level between the dc output level of a continuous mark frequency and the dc output level of a continuous space frequency). This external adjustment on RXB also balances possible internal offsets. (for RXB adjustment procedure see page 4-15). The output of the comparator is then available at the RXD output. carrier detector The carrier detect circuitry comprises an energy detector and digital delay. The energy detector and digital delay. The energy detector compares the total signal level at the output of the receive filter to an externally set threshold on the CDL pin. If there is a loss of carrier singal then CDT (carrier status flag) will not go low during a time delay fixed by the digital delay. If, however this fixed time has elapsed and the carrier is still not present then CDT goes low and "carrier fail" is indicated. The carrier detector also has a minimum 2 dbm hysteresis to avoid oscillations on CDT when the receive level is close to the carrier detect threshold. timing and control An on-chip oscillator runs from an external 4.4336 MHz PAL crystal connected between OSC1 and OSC2 or an external signal driving OSC1. A clock signal equal to 16 times the highest selected bit rate (transmit or receive) is available on the CSK pin. The single supply implies that all analogue functions be referenced to an internally generated voltage. All analogue inputs and outputs must be a.c. coupled. or d.c. bias must be adapted. receive/transmit modes of operations STANDARD TRS TXR1 TXR2 TRANSMITTED RECEIVED CLK BIT RATE (b/s) BIT RATE (b/s) FREQUENCY(KHz) 0 0 0 1200 1200 19.11 1 0 0 1200 75 19.11 0 0 1 600 75 9.56 1 0 1 600 600 9.56 CCITT V23 0 1 0 75 1200 19.11 1 1 0 75 600 9.56 0 1 1 75 75 1.19 ___ CLK* 0 0 1200 1200 19.11 CLK 8 0 1 1200 150 19.11 CLK 8 0 1 1200 5 19.11 BELL202 CLK 1 0 150 1200 19.11 CLK 1 1 150 150 2.39 See note 1 1 See note 1 5 1200 19.11 1 1 1 Transmit 1200 19.11 disabled FIG. 5 Clock output must be inverted and connected to TRS input. NOTE 1 : In this mode the modulation is controlled by the TRS and TXR2 TRS = CLK & TXR2 = 0 TXD = 1 TXA = 387Hz TRS = 1 & TXR2 = 1 TXD = 1 or 0, TXA = 0Hz TCM 3105 PAGE 9 (4-13) FSK MODEM frequency assignment STANDARD TRANSMITTED TXD TRANSMITTED BIT RATE b/s FREQUENCY Hz 75 1 M 390 75 0 S 450 600 1 M 1300 CCITT V23 600 0 S 1700 1200 1 M 1300 1200 0 S 2100 150 1 M 387 150 0 S 487 1200 1 M 1200 BELL 202 1200 0 S 2200 5 See note 1 M 387 S 0 FIG.6 NOTE 1 : In this mode the modulation is controlled by the TRS and TRX2 inputs TRS = CLK & TXR2 = 0 TXD = 1 TXA = 387 Hz TRS = 1 & TXR2 = 1 TXD = 1 or 0 TXA = 0 Hz TCM 3105 PAGE 10 (4-14) FSK MODEM (4-15) typical applications circuits 2W/4W converter for +5V single supply operation (gives maximum dynamic range of signal on line when only +5V is available). FIG.8, FIG.9 See 3105_8.sch, 3105_9.sch (OrCAD SDT schematic file) important application notes 1. AUTOMATIC GAIN CONTROL Automatic gain control will initially be set to maximum gain when no signal is received The gain will then be reduced in steps (up to 16, it high level is received) on each consecutive mark received. Consequently an adjustment delay up to 11 ms should be provided by a continuous "Mark" signal (N.B. 11 ms would be required in the case of peak voltage of input waveform to AGC being at maximum dynamic range of AGC). This procedure will normally be followed such that the adjustment delay occurs along with carrier detect and precautions should be taken when deciding upon setting up and testing method. 2. CDL APJUSTMENT For optimum results. CDL should be adjusted to the following ratios of VDD: min = VDD x 0 60 typ = VDD x 0.70 max = VDD x 0.80 3. RXB ADJUSTMENT PROCEDURE The choice of d-c voltage on the RXB input (pin 7), determines the decision threshold of the final comparator stage of the receive circuitry. Correct adjustment is achieved by : (i) first applying a constant mark frequency to the receiver (RXA input) for a minimum duration of 11 ms. (ii) Then applying a continuous 101...... pattern while RXB input voltage is adjusted to give an RXD output signal with a 50 % duty cycle. min = VDD x 0.45 typ = VDD x 0 55 max = VDD x 0.65 Scanned & digital remastered by HG5CDU (Lancelot) 1993.10.13. Based on Texas Instruments Interface Circuits book from HG5CES (Csuhi) ( More info Csuhi )